1. Field of the Invention
The invention relates to gold plating of conductor traces on printed circuit boards and the like. More particularly, the invention relates to electroless gold plating of copper conductors on printed circuit boards and the like for use in connection with bare die attach integrated circuit devices.
2. Description of the Related Art
Printed circuit boards (PCBs) upon which integrated circuits (ICs) are mounted are well known. Printed circuit boards can be made of various materials, including, but not limited to, epoxy glass and polyimide glass. Traditionally, encapsulated IC chips are mounted on substrates such as PCBs with lead fingers, which protrude from the encapsulated ICs, attached to conductive bond sites on the PCB in order to provide electrical paths between the PCB and circuitry within the IC chips. The bond sites on the PCB are electrically part of or are coupled to conductive traces that lead to other circuitry on the PCB and/or to contacts on the edges of the PCB for coupling to off-PCB circuitry. More recently, however, fabrication techniques are being used in which bare dies (i.e., not encapsulated) are bonded directly to PCBs. The bond pads on the top surface of the dies are then wire bonded to the bond sites on the PCB in essentially the same fashion that bond pads on dies are wire bonded to lead frames in traditional, encapsulated IC chips.
There are several well known bare die attach techniques and assemblies, including assemblies commonly known as multichip (MCMs) and chip-on-board (COB) assemblies. FIG. 1 is a cross-sectional side view of an exemplary chip-on-board assembly 1. The assembly comprises a PCB 2 on which a bare die 3 has been adhered. Bond pads on the top die surface have been wirebonded to contacts on the PCB by wirebonds 4. Finally the die, including the wirebonds 4, has been encapsulated within encapsulant 5 right on the PCB.
These direct die attach assemblies as well as others typically require that the conductive traces, contact points and vias on the PCB be formed of gold plated copper. The gold plating must be of sufficient quality (having fine, uniform grains) and thickness (nominally 0.5 microns, which is about 20 micro-inches) to ensure excellent wire bondability and reliability during long term operation.
Further, for bare die attach techniques, the copper on the PCB must be patterned prior to the gold plating process since gold and copper generally cannot be etched simultaneously with the same etchant. Consequently, performing the copper etching after the gold etching would undermine the gold layer and leave gold cantilevered over the copper, which is not an acceptable condition. Since the boards are patterned before the gold plating process, there typically will not be a continuous circuit path comprising all of the copper on the PCB and, thus, it is impossible, or at least impractical, to gold plate the copper by electroplating techniques. Accordingly, for bare die attach integrated circuits (as well as other integrated circuits), the gold plating process typically is an electroless process, i.e., either immersion, autocatalytic or both. In addition, it typically is desirable to form a barrier layer between the copper and the gold to prevent migration of the copper into the gold and also to ensure excellent adhesion of the gold to the copper.
Multi-layer printed circuit boards commonly include conductively plated through holes to provide interconnection between conductive traces on the various layers of the board. Such through holes may run completely through the PCB assembly from one surface to the opposite surface and, thus, be open at both ends. However, techniques are now well established for providing blind vias in multi-layer printed circuit boards. Blind vias are open at one end but terminate short of the opposite surface of the PCB at one of the intermediate layers. Blind vias conserve real-estate on the circuit board since they do not consume space on layers on which they do not serve an electrical function. Also in furtherance of the ever present desire to reduce the size of circuitry, it is desirable for the through holes and blind vias to have as small a diameter as possible. Particularly, blind vias with diameter to depth aspect ratios of 1:1 up to 1:5 or greater are known in the prior art. However, it has been found to be rather difficult to electrolessly gold plate blind vias with aspect ratios of 1:1 or greater. Particularly, it is difficult to guarantee that sufficient exchange of the electroless nickel and/or gold plating solutions into and out of the blind vias to fully plate the surfaces of the blind vias.
Therefore, it is an object of the present invention to provide a new and/or improved technique for electroless gold plating of conductive traces on printed circuit boards and the like.
The invention is a technique for electrolessly gold plating copper patterns on a PCB or the like that is particularly suited for use in connection with the manufacture of PCBs upon which bare dies will be mounted. Starting with a printed circuit board (PCB) with patterned copper on its surface and in any vias, one particular, complete process in accordance with the current embodiment of the present invention comprises the following steps:
1. Cleaning the PCB in a bath of cleaning solution with the application of ultrasonic agitation with the PCB initially oriented vertically and gradually moved to a 45xc2x0 angle to the ground followed by rinsing in a high pressure rinse with de-ionized water;
2. Immersing the PCB in a 10% solution of sulfuric acid with the application of ultrasonic and mechanical agitation (if the conductor spacing is less then 5 mils, the solution is reduced to approximately 1 to 5% sulfuric acid);
3. Rinsing in overflowing de-ionized water;
4. Immersing the PCB in a 5% solution of sulfuric acid with the application of ultrasonic and mechanical agitation. This second sulfuric acid wash preferably is not followed by a rinse;
5. Plating the copper with palladium by immersing the PCB in a palladium activation solution at approximately 30xc2x0 C. with the application of ultrasonic agitation for 5 seconds at 30 second intervals. The PCB should be initially positioned at a 45xc2x0 angle and be flipped approximately half way through the process to the opposing 45xc2x0 angle;
6. Rinsing with de-ionized water in an overflowing beaker for approximately 30 seconds;
7. Post dipping in a 1% solution of sulfuric acid to help eliminate bridge plating;
8. Rinsing in overflowing de-ionized water;
9. Immersing in a bath of electroless nickel at approximately 80xc2x0 C. without ultrasonic agitation, but with mechanical agitation;
10. Rinsing in overflowing de-ionized water;
11. Nitrogen blow drying;
12. Visually inspecting for full nickel coverage of the copper;
13. Immersing in an approximately 30% solution of hydrochloric acid with manual agitation, followed by a overflowing de-ionized water rinse
14. If full nickel coverage was not achieved, repeating steps 4 through 13;
15. Immersing in a gold flash plating solution at approximately 90xc2x0 and a pH of 4.5 to 4.7 to establish a first thin layer of electroless gold;
16. Rinsing in overflowing de-ionized water;
17. Immersing in an autocatalytic gold plating bath at approximately 70xc2x0 C. for sufficient time to achieve the desired over all gold thickness;
18. Rinsing in overflowing de-ionized water;
19. Blow drying with dry nitrogen.